LHF08CTE
3
1 INTRODUCTION
This datasheet contains LH28F008SCHT-TE
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SCHT-TE
Flash memory documentation also includes
application notes and design tools which are
referenced in Section 7.
1.1 New Features
The LH28F008SCHT-TE SmartVoltage Flash
memory maintains backwards-compatibility with
SHARP’s 28F008SA. Key enhancements over the
SmartVoltage technology provides a choice of V CC
and V PP combinations, as shown in Table 1, to meet
system performance and power expectations. 2.7V
V CC consumes approximately one-fifth the power of
5V V CC . But, 5V V CC provides the highest read
performance. V PP at 3.3V and 5V eliminates the need
for a separate 12V converter, while V PP =12V
maximizes block erase and byte write performance.
In addition to flexible erase and program voltages,
the dedicated V PP pin gives complete data protection
when V PP ≤ V PPLK .
Table 1. V CC and V PP Voltage Combinations
Offered by SmartVoltage Technology
V CC Voltage V PP Voltage
2.7V (1) ?
28F008SA include:
3.3V
5V
3.3V, 5V, 12V
5V, 12V
Internal V CC and V PP
? SmartVoltage Technology
? Enhanced Suspend Capabilities
? In-System Block Locking
Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
28F008SA to LH28F008SCHT-TE. When upgrading,
it is important to note the following differences:
? Because of new feature support, the two devices
have different device codes. This allows for
software optimization.
? V PPLK has been lowered from 6.5V to 1.5V to
support 3.3V and 5V block erase, byte write, and
lock-bit configuration operations. The V PP voltage
transitions to GND is recommended for designs
that switch V PP off during read operation.
? To take advantage of SmartVoltage technology,
allow V PP connection to 3.3V or 5V.
1.2 Product Overview
The LH28F008SCHT-TE is a high-performance
8M-bit SmartVoltage Flash memory organized as
1M-byte of 8 bits. The 1M-byte of data is arranged in
sixteen 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
NOTE:
1. Block erase, byte write and lock-bit configuration
operations with V CC <3.0V are not supported.
detection Circuitry
automatically configures the device for optimized
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, byte write, and lock-bit configuration
operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.3s (5V V CC , 12V
V PP ) independent of other blocks. Each block can be
independently erased 100,000 times (1.6 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in byte increments
typically within 6μs (5V V CC , 12V V PP ). Byte write
suspend mode enables the system to read data or
execute code from any other flash memory array
location.
memory map is shown in Figure 3.
Rev. 1.3
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